What the board presents to the CPU
The complete board supplies 65,536 byte locations on a 16-bit address bus. Each of its 32 DRAMs stores 16,384 bits. Eight chips operating in parallel form one 16 KB byte-wide bank; four banks provide 64 KB. This is fixed jumper mapping within the 64 KB space, not software bank switching beyond it.
The S-100 data paths are separate: CPU DO0–DO7 enter buffers and become MDO0–MDO7, the DRAM write inputs. DRAM outputs MDI0–MDI7 go into IC12, whose outputs drive CPU DI0–DI7. “DO” and “DI” are named from the processor's point of view.
The four physical chip rows are A (top), B, C and D (bottom). Their RAS numbers run in the opposite order: A uses /RAS3, B /RAS2, C /RAS1, and D /RAS0. Within any bank, chip suffix 0 stores bit 0, suffix 7 bit 7. Shared data outputs require that ordinary accesses activate only one bank.
References: supplied manual, PDF pages 17–20, drawings A1066–A1069. A slash in this guide means active-low; the internal signals named RAS and CAS on A1065 are active-high, before the final inversion/decoding.
The address is multiplexed—and inverted
Each DRAM has only seven address pins, MA0–MA6. It latches a seven-bit row on the falling edge of /RAS, then a seven-bit column on the falling edge of /CAS. IC19, the Intel 3242, supplies these two words or its internal refresh count. Its outputs invert the input address bits. The board also routes CPU A13 to the multiplexer’s row input A6, and CPU A6–A12 to its seven column inputs. Intel 3242 datasheet.
| DRAM pin bus | Row phase (ROW SEL = 1) | Column phase (ROW SEL = 0) |
|---|---|---|
| MA0–MA5 | NOT CPU A0–A5 | NOT CPU A6–A11 |
| MA6 | NOT CPU A13 | NOT CPU A12 |
r = (address & 0x3F) | ((address >> 7) & 0x40) c = (address >> 6) & 0x7F physical row = r XOR 0x7F physical column = c XOR 0x7F
At 5A3C, r = 3C and c = 68. The actual address pins carry 43 at /RAS, then 17 at /CAS. At 5A7C, only A6 changes; it changes the column, not the row. At 7A3C, A13 changes; it changes the row’s high bit. Inversion changes physical placement but never complements the stored data byte.
Why put A13 in the row word? A one-to-one permutation of the 14 within-bank address bits preserves capacity and ordinary random-access behavior; the 3242’s inversion does too. Easier PCB routing is a plausible explanation for this choice, particularly with the S-100 connector pin order, but the schematic does not establish the designer’s reason. Swapping row and column assignments would change locality for page/static-column schemes; this board’s normal cycle switches and strobes both words for every access. There is no evidence here of such an optimized access mode.
The 3242 is labeled “14” inside its symbol on A1066, conflicting with the LS244 IC14 on that same sheet. The parts layout identifies the 3242 as IC19; that is the designation used here.
Which bank responds, and where memory disappears
IC25, a 74LS156 dual decoder, decodes A15:A14 into four active-low 16 KB block signals. Jumper-selected outputs pull down the top or bottom selection buses. These are open-collector outputs, so tying selected decoder outputs together is intentional. The 10 kΩ resistors pull the buses high when no selected output is active. A push-pull decoder would not be an equivalent replacement. TI 74LS156 datasheet.
One decoder section also selects a block in which IC24 decodes A13:A11 into eight 2 KB segments. A deselect jumper suppresses the board in that segment. IC21 and IC20 combine address selection, the hole mask, and PHANTOM. Pulling PHANTOM low disables the board; its 10 kΩ pull-up normally permits operation.
selected = (top match OR bottom match)
AND NOT selected 2 KB hole
AND PHANTOM high
/WE = NOT (MEMW AND selected)
/OE(IC12) = NOT (DBIN AND MEMR AND selected)16/32 KB mode: straps 2 and 4 make a top-group match select bank A and a bottom-group match bank B. Each populated bank can therefore be placed at any one 16 KB boundary.
48/64 KB mode: straps 1 and 3 make A14 select one of two banks within a pair. TOP ROWS is the bottom-selection bus: it is high for a top-pair access and low for a bottom-pair access. IC22 decodes that signal and A14. A standard complete map is:
| Address block | Jumpers | A14 | Physical bank |
|---|---|---|---|
| 0000–3FFF | Top 0 | 0 | B / RAS2 |
| 4000–7FFF | Top 1 | 1 | A / RAS3 |
| 8000–BFFF | Bottom 2 | 0 | D / RAS0 |
| C000–FFFF | Bottom 3 | 1 | C / RAS1 |
This explains the manual’s adjacent-pair rule: 0+1, 1+2, 2+3 or 3+0 gives one even and one odd block. Selecting 0+2 for a pair sends both blocks to the same physical bank and aliases them. For a 48 KB board’s remaining 16 KB, an even block needs chips in physical D; an odd block needs physical C. Overlapping top and bottom selections are not an independent double-bank feature: the bottom bus controls the pair selection.
Example: SOL-20. Set the deselect block to 3 and the segment mask to 0 and 1. C000–C7FF and C800–CFFF stop responding; D000–FFFF remains available. A disabled area returns high impedance, not a guaranteed FF value. Another board or bus pull-ups determine what the CPU sees.
With the manual’s 2650 “C” header arrangement, the block decoder uses A14:A13 instead, giving 8 KB boundaries. The special OPREQ and clock wiring also differs. The interactive model deliberately does not emulate a 2650 bus master.
How an access becomes a timed DRAM cycle
IC15 and IC16 are wired DIP headers, not active ICs. They adapt CPU timing and select the upper address inputs. With the standard 8080 header connections, ACC TRIG = MEMW OR (PCLK AND SYNC AND MDO7). Version 1 omitted MDO7 from that sentence. MDO7 is the buffered status bit on DO7 during SYNC, not the high bit of an instruction opcode. IC18’s fourth AND input is tied high. MDO7 goes through header pins 16→1 to IC18 pin 9, PCLK through 13→4 to pin 10, and SYNC through 14→3 to pin 12. The Z80 header uses MEMR for its read trigger. PCLK normally comes from inverted Φ2; the manual lists alternate Z80 clock arrangements. IC4 samples M1 at PCLK to make M1 CYC.
Why qualify the 8080 status pulse? A latched MEMR status can remain high across consecutive memory-read cycles. The PCLK/SYNC/status-byte combination supplies a fresh qualified request and a release interval for IC9 to rearm. That explains a useful electrical distinction from simply feeding a held MEMR level into the trigger. It is a circuit-level explanation, not a documented statement of the designer’s intent. The Z80 header assumes a compatible supplied MEMR waveform that releases between requests; the Z80 does not emit the 8080 status byte.
- Start. IC9 and the fast NAND gates of IC10 turn an access assertion into one TRIG pulse. At Δ1 the trigger latch suppresses further pulses until that request is released. An extended CPU request must not cause repeated writes.
- Row strobe. TRIG sets the first half of IC3, raising internal RAS. IC22 and IC23 pull only the selected bank’s /RAS low. The seven row bits were already present.
- Address switch. IC26 detects that a physical /RAS has fallen. IC20’s selectable inverter chain and IC17 then lower ROW SEL after a delay. IC19 switches from row to column data, preserving row-address hold time first.
- Column strobe. Delay-line tap Δ1 clocks the other half of IC3. Internal CAS rises; IC10 drives the common /CAS0–3 low. The active bank now has a complete cell address.
- Data. A read produces one bit per chip on MDI0–7. A write uses buffered MDO0–7 with /WE low; data must satisfy the installed DRAM’s setup and hold requirements around the write-latching edge.
- Capture and finish. Δ3, its delayed versions, IC4 and the timing straps terminate RAS/CAS. IC12 preserves the read byte after the DRAM outputs release. CYC END also gives the refresh controller a scheduling point. Precharge is required before another RAS pulse.
With a 74LS373 at IC12, its latch-enable is effectively NOT REF CYC AND selected AND RAS: it follows valid DRAM data while enabled and holds it when the window closes. A 74LS374 instead samples on a positive edge derived from Δ3 DELAYED. Straps 12/13 must match the installed part. TI 373/374 datasheet.
The latch’s capture control is separate from its bus output enable. Refresh inhibits capture but is not an input to /OE. During a long selected CPU read, IC12 can keep driving the previously captured byte while the DRAM array is refreshed. Refresh need not force the S-100 data bus to high impedance.
The manual specifies board access times of 450 ns maximum for the 2 MHz board and 250 ns maximum for the 4 MHz board, a listed cycle time of 480 ns maximum, no generated wait states, and DMA at 1 MHz maximum. Those are board specifications, not measured timings here. The text calls for 4116-25 and 4116-20 respectively; the older array drawing says 2117-4 or equivalent. Starred logic positions require 74S parts for the 4 MHz version. Changing only the RAM speed grade does not establish 4 MHz operation.
The STTLDM-401 is drawn with delay taps Δ1, Δ3 and Δ4. Its timing-delay role is inferred directly from that symbol and the connected strobe/capture logic. No manufacturer datasheet or tap-delay/tolerance table has been established. “401” is not evidence for a particular delay. A contemporary ETI reviewer (October 1979, p. 155) also inferred its role; that is corroboration of an interpretation, not an official component specification. Straps 5–8 choose end/capture timing; straps 9–11 choose the address-switch delay. The simulator therefore shows phases rather than fabricating exact strobe widths.
Refresh is a second user of the same array
A DRAM read senses and restores an entire internal row even though only one column is presented as data. The 2117 family requires all 128 row addresses to be refreshed within 2 ms. A uniformly serviced 15 µs row interval gives 128 × 15 µs = 1.920 ms, leaving 80 µs against that full-array retention requirement. The manual lists a 15 µs maximum refresh period, but an oscillator/request period alone does not prove that service meets it. Arbitration latency, coalesced requests and pauses matter. Measure the maximum interval between services of each row, not just the oscillator frequency. It is not a claim that an entire array sweep takes 15 µs. Intel 2117 datasheet.
Three Schmitt inverters in IC11, an 82 Ω resistor and a 0.1 µF capacitor form a free-running oscillator. Its edge sets the pending-refresh latch in IC6, producing ALLOW REF. The RC product is 8.2 µs, but that alone is not the oscillator period; thresholds and propagation matter.
At CYC END, the other IC6 flip-flop samples NOT(M1 CYC AND ALLOW REF). A pending request at an instruction-fetch opportunity makes REF CYC high. It clears the request latch, selects IC19’s internal refresh address, and starts a timed refresh operation through IC9/IC10. At completion, REF CYC drops and the 3242 count input advances the row counter. This is a board-local address counter, not the Z80’s refresh-address register.
IC1, a 74LS161, is a watchdog for prolonged waits or reset. Both count enables receive ALLOW REF; its active-low load is NOT(RDY AND /RST), with parallel inputs tied to zero. During normal ready operation it repeatedly loads zero. When RDY or /RST is low, it can count pending-request PCLK edges. Terminal count 15 asserts FORCE REF through IC7, independently forcing the refresh flip-flop into its refresh state. REF CYC then clears the counter. It is not simply a free-running divide-by-16 refresh generator. TI 74LS161 datasheet.
This explains reset straps 14/15: pin 75 or pin 99 must supply the reset signal appropriate to the host. The manual specifically connects a wrong choice with failure to retain data through reset. Power and the required PCLK activity must remain available; this is not battery-backed memory.
/REF RAS = NOT (REF CYC AND internal RAS) /RAS(bank) = IC22 bank output AND /REF RAS
During refresh, /REF RAS goes low and all four /RAS outputs are forced low through IC23, overriding normal memory selection. Even holes and PHANTOM-disabled areas are restored. Normal reads and writes also refresh their addressed row, but a CPU loop touching a small area does not replace systematic refresh.
A1065 takes the CAS flip-flop’s D input to +5 V and clocks it from Δ1. Its common /CAS output has no visible REF CYC inhibition. A1067 simultaneously asserts all four /RAS lines during refresh, and A1068 joins the four banks’ corresponding data outputs. With /WE high and the shown RAS/CAS sequence, the banks perform full read-type refresh together. A read restores the row just as refresh requires. Their corresponding outputs share the MDI wires, so different stored bits create opposing drivers. Equal bits do not oppose one another, and uninitialized/expired model data means an unknown result rather than proof of opposing values. Blocking IC12 capture protects the saved CPU byte but does not remove contention on the internal MDI wires.
The /WE gate also has no explicit REF CYC input. If a selected MEMW remained asserted into a refresh with CAS active, the literal logic could enable a write in multiple banks. Check MEMW and /WE alongside the refresh strobes, especially during waits; the supported CPU timing may be essential to avoiding this overlap.
Version 2 explicitly resolves each MDI bit as 0, 1, Z or X and separately reports a known opposing-driver mask. Z drivers leave the RA01 pull-ups to resolve the bus high. X is a logical uncertainty marker, not a predicted voltage. The 3242 refresh selection overrides ROW SEL through both strobes, so the selected physical column equals the refresh row: the read samples a diagonal cell in each bank. IC12 retains its byte because its capture is inhibited. A held qualified CPU read can still enable IC12’s output. Currents, heating, output impedance and exact overlap duration are not modeled. Check a real board’s CAS waveform, modifications and exact DRAM type before deciding whether the drawing omits a detail. Intel recommends RAS-only refresh for wired-common DRAM outputs. This is a specific verification target, not proof that every shipped board is defective.
HALT is not the same as wait or reset
On IC1, /LOAD = NOT(RDY AND /RST), and all four parallel data inputs are zero. When RDY and /RST are high, /LOAD is low and each PCLK rising edge loads zero even if a refresh is pending. When either input is low, the pending request enables counting. Carry appears at count 15, forces REF CYC, then the feedback asynchronously clears IC1 and the pending latch. This is 15 enabled edges from zero, not a sixteenth-edge overflow. New oscillator edges during active refresh are masked by the request latch’s clear.
| Host condition | Normal opportunity | IC1 fallback | Expected implication |
|---|---|---|---|
| 8080 HALT after residual cycles | No further M1 fetch opportunities | None if RDY and /RST stay high | A pending request can remain unserviced; retention is not assured. |
| Z80 HALT with compatible bus board | Repeated M1 cycles; fetched data ignored | Usually not needed | Normal arbitration can continue. This board does not use the Z80 R register. |
| Wait: RDY low | May be delayed | Pending + continuing PCLK → count 15 | Forced refresh remains possible. |
| Reset: /RST low | May be absent | Pending + continuing PCLK → count 15 | Correct reset strap and PCLK matter. |
| PCLK stopped | No new sampled CPU opportunity | No new counter edges | Free-running request oscillator alone cannot sustain refresh. |
The 8080’s WAIT output is not the same signal as the RDY input. A host may choose to drive RDY low during HALT or front-panel stop, changing the result. An already-started cycle or sampled M1 may cause residual activity after a mode change. HOLD/DMA, front-panel stop, wait, reset and CPU HALT need their actual host waveforms checked individually. The presets state assumptions; they do not claim to emulate every S-100 CPU board.
Zilog Z80 CPU User Manual, HALT description (printed p. 14), describes repeated M1 cycles in HALT. The reproduced Intel 8080 material in the Altair 8800b manual documents the status word and HALT sequence (printed pp. 2-26 and 2-34).
Component index
| Reference | Device | Role in this board |
|---|---|---|
| IC1 | 74LS161 | Pending-refresh timeout during wait/reset; terminal carry forces refresh. |
| IC2 | 74LS00 | Refresh state logic, refresh RAS and reset/ready qualification. |
| IC3 | 74S74 | Separate active-high RAS and CAS state flip-flops. |
| IC4 | 74S74 | M1 sampling and delayed cycle termination. |
| IC5 | Spare | No active function shown. |
| IC6 | 74S74 | Pending refresh and active refresh state. |
| IC7 | 74LS04 | Δ3 delay stages and FORCE REF inversion. |
| IC8 | STTLDM-401 | Tapped timing delay for the internal memory cycle. |
| IC9 | 74LS74 | Access/refresh trigger pulse shaping and rearming. |
| IC10 | 74S00 | Fast trigger combining and CAS inversion/drive. |
| IC11 | 74LS14 | RC refresh oscillator. |
| IC12 | 373 or 374 | Eight-bit read holding register and tri-state bus output; LS or S as specified. |
| IC13 | 74LS10 | Separate read-output enable and latch-capture qualification. |
| IC14, IC27 | 74LS244 | Address/control and write-data buffering; IC14 also handles DO7. |
| IC15, IC16 | Wired headers | Processor clock, trigger, and address-boundary adaptation. |
| IC17 | 74LS14 | Clock/MEMW inversion and final ROW SEL shaping. |
| IC18 | 74S20 | Combines processor read timing and MEMW into ACC TRIG. |
| IC19 | Intel 3242 | Inverting row/column/refresh multiplexer and 7-bit refresh counter. |
| IC20 | 74LS04 | Select inversion and adjustable delay before changing row to column. |
| IC21 | 74LS10 | Block/hole/PHANTOM selection and DRAM /WE. |
| IC22 | 74LS138 / 74S138 | Selects one of four physical bank RAS paths. |
| IC23 | 74LS08 | Four AND gates combine bank RAS with forced refresh RAS. |
| IC24, IC25 | 74LS156 | 2 KB deselection and main address decoding; open-collector jumper buses. |
| IC26 | 74LS13 | Detects any asserted physical RAS for address-switch timing. |
| A0–D7 | 2117 / 4116 family | 32 one-bit-wide DRAMs in four eight-chip banks. |
| RA01 | 10 kΩ resistor pack | Pulls up the eight internal MDI lines when DRAM outputs release. |
DRAM supplies on A1068 are +5 V on pin 9, +12 V on pin 8, −5 V on pin 1, and ground on pin 16. The placement sheet shows 7805 and 7812 regulators, a 1N4733 zener, a 680 Ω resistor, bulk capacitors and local bypass capacitors. The zener/resistor are consistent with producing the negative bias supply, but these five sheets do not contain a complete power-supply wiring schematic. Verify the actual negative-rail circuit rather than inferring every connection from placement.
Decoupling matters because many DRAM sense amplifiers switch together, especially when all banks refresh. Power faults can look like data or timing faults. Board insertion/removal and component changes must be done with power removed and supplies discharged, as the manual specifies.
A practical sequence of tests
First record the fitted DRAM type, IC12 type, speed version, IC15/16 header wiring, straps 1–15 and all address/hole jumpers. The schematic depicts alternatives, not one universally correct strap configuration.
- Verify supplies at the DRAM pins. Confirm +5, +12 and −5 V relative to pin 16, then check ripple during accesses and refresh. Check the installed part’s voltage tolerances.
- Check decode at boundaries. Probe MEM SEL’D at 3FFF/4000, 7FFF/8000 and BFFF/C000. For a SOL-20 hole, also check C7FF/C800 and CFFF/D000. PHANTOM low should disable external access without stopping refresh.
- Single write/read. Write A5 to 5A3C, read back A5; then try 5A. Under the standard 64 KB map, only /RAS3 should assert on ordinary accesses. MA should change from 43 to 17. /WE goes low on the write; IC12 /OE is low only during the qualified read.
- Test data bits. Write 01,02,04,08,10,20,40,80 and complements at safe locations in every bank. A repeatable bit failure in one bank implicates that bank’s corresponding DRAM/socket; the same bit across all banks points toward shared MDO, MDI, buffers or IC12.
- Test address independence. Use address-dependent patterns and walking address bits. Compare 5000/5040 for A6 and 5000/7000 for A13. Compare 1234,5234,9234,D234 with values 11,22,33,44 to expose bank aliasing.
- Test retention without refreshing the target by reading it. Fill the target, execute elsewhere for several milliseconds, and only then verify. Repeat with reset and a supported wait condition. A tight read loop at the tested addresses can mask a broken refresh system.
- Probe the refresh chain. Check oscillator edges, ALLOW REF, M1 CYC, CYC END, REF CYC, IC1 carry, and IC19 RF/count. During REF CYC inspect all four /RAS lines and the common /CAS line together. Confirm that 128 distinct row addresses are serviced within the installed DRAM’s refresh requirement.
- Separate HALT, wait, reset and stopped-clock tests. Record RDY, /RST, PCLK, M1 CYC, CYC END, ALLOW REF, IC1 /LOAD and carry together. Ignore initial residual activity: look for sustained row-counter advance. An asserted WAIT output does not establish RDY low.
- Expose refresh contention. In a controlled bench test, contrast banks with opposing data patterns rather than filling every bank identically. Observe MDI during common RAS/CAS and confirm IC12 capture inhibition independently of /OE. The simulator fixture demonstrates the logic; it cannot estimate electrical stress. Also inspect MEMW and /WE through extended waits for any overlap with refresh.
- Measure margins. Verify row/column setup and hold, RAS/CAS pulse widths, precharge and IC12 capture relative to data validity using the fitted parts’ datasheets. “No wait states” assumes a compatible CPU bus waveform; it is not permission for arbitrary DMA timing.
The manual’s 8080 test lives in known-good RAM at 0000 and normally tests 4000–7FFF. It writes and verifies a changing byte pattern, offsets it and repeats. On failure it stores the read byte at 0000, expected byte at 0001, low failing-address byte at 0002 and high byte at 0003, then halts. For 32 KB, the manual changes the end comparison bytes at 0016 and 002C to C0. Avoid testing over the running program, stack or active ROM mappings. The printed 2650 test has separate STARTT/ENDT limits and runs from display memory.