Inside the 64K
dynamic RAM board.

What the board presents to the CPU

The complete board supplies 65,536 byte locations on a 16-bit address bus. Each of its 32 DRAMs stores 16,384 bits. Eight chips operating in parallel form one 16 KB byte-wide bank; four banks provide 64 KB. This is fixed jumper mapping within the 64 KB space, not software bank switching beyond it.

The S-100 data paths are separate: CPU DO0–DO7 enter buffers and become MDO0–MDO7, the DRAM write inputs. DRAM outputs MDI0–MDI7 go into IC12, whose outputs drive CPU DI0–DI7. “DO” and “DI” are named from the processor's point of view.

The four physical chip rows are A (top), B, C and D (bottom). Their RAS numbers run in the opposite order: A uses /RAS3, B /RAS2, C /RAS1, and D /RAS0. Within any bank, chip suffix 0 stores bit 0, suffix 7 bit 7. Shared data outputs require that ordinary accesses activate only one bank.

References: supplied manual, PDF pages 17–20, drawings A1066–A1069. A slash in this guide means active-low; the internal signals named RAS and CAS on A1065 are active-high, before the final inversion/decoding.

The address is multiplexed—and inverted

Each DRAM has only seven address pins, MA0–MA6. It latches a seven-bit row on the falling edge of /RAS, then a seven-bit column on the falling edge of /CAS. IC19, the Intel 3242, supplies these two words or its internal refresh count. Its outputs invert the input address bits. The board also routes CPU A13 to the multiplexer’s row input A6, and CPU A6–A12 to its seven column inputs. Intel 3242 datasheet.

r = (address & 0x3F) | ((address >> 7) & 0x40)
c = (address >> 6) & 0x7F
physical row = r XOR 0x7F
physical column = c XOR 0x7F

At 5A3C, r = 3C and c = 68. The actual address pins carry 43 at /RAS, then 17 at /CAS. At 5A7C, only A6 changes; it changes the column, not the row. At 7A3C, A13 changes; it changes the row’s high bit. Inversion changes physical placement but never complements the stored data byte.

The 3242 is labeled “14” inside its symbol on A1066, conflicting with the LS244 IC14 on that same sheet. The parts layout identifies the 3242 as IC19; that is the designation used here.

Which bank responds, and where memory disappears

IC25, a 74LS156 dual decoder, decodes A15:A14 into four active-low 16 KB block signals. Jumper-selected outputs pull down the top or bottom selection buses. These are open-collector outputs, so tying selected decoder outputs together is intentional. The 10 kΩ resistors pull the buses high when no selected output is active. A push-pull decoder would not be an equivalent replacement. TI 74LS156 datasheet.

One decoder section also selects a block in which IC24 decodes A13:A11 into eight 2 KB segments. A deselect jumper suppresses the board in that segment. IC21 and IC20 combine address selection, the hole mask, and PHANTOM. Pulling PHANTOM low disables the board; its 10 kΩ pull-up normally permits operation.

selected = (top match OR bottom match)
           AND NOT selected 2 KB hole
           AND PHANTOM high
/WE = NOT (MEMW AND selected)
/OE(IC12) = NOT (DBIN AND MEMR AND selected)

16/32 KB mode: straps 2 and 4 make a top-group match select bank A and a bottom-group match bank B. Each populated bank can therefore be placed at any one 16 KB boundary.

48/64 KB mode: straps 1 and 3 make A14 select one of two banks within a pair. TOP ROWS is the bottom-selection bus: it is high for a top-pair access and low for a bottom-pair access. IC22 decodes that signal and A14. A standard complete map is:

This explains the manual’s adjacent-pair rule: 0+1, 1+2, 2+3 or 3+0 gives one even and one odd block. Selecting 0+2 for a pair sends both blocks to the same physical bank and aliases them. For a 48 KB board’s remaining 16 KB, an even block needs chips in physical D; an odd block needs physical C. Overlapping top and bottom selections are not an independent double-bank feature: the bottom bus controls the pair selection.

Example: SOL-20. Set the deselect block to 3 and the segment mask to 0 and 1. C000–C7FF and C800–CFFF stop responding; D000–FFFF remains available. A disabled area returns high impedance, not a guaranteed FF value. Another board or bus pull-ups determine what the CPU sees.

With the manual’s 2650 “C” header arrangement, the block decoder uses A14:A13 instead, giving 8 KB boundaries. The special OPREQ and clock wiring also differs. The interactive model deliberately does not emulate a 2650 bus master.

How an access becomes a timed DRAM cycle

IC15 and IC16 are wired DIP headers, not active ICs. They adapt CPU timing and select the upper address inputs. With the standard 8080 header connections, the read part of ACC TRIG is PCLK AND SYNC; MEMW also triggers an access. The Z80 header uses MEMR for its read trigger. PCLK normally comes from inverted Φ2; the manual lists alternate Z80 clock arrangements. IC4 samples M1 at PCLK to make M1 CYC.

1. Start. IC9 and the fast NAND gates of IC10 turn an access assertion into one TRIG pulse. At Δ1 the trigger latch suppresses further pulses until that request is released. An extended CPU request must not cause repeated writes.
2. Row strobe. TRIG sets the first half of IC3, raising internal RAS. IC22 and IC23 pull only the selected bank’s /RAS low. The seven row bits were already present.
3. Address switch. IC26 detects that a physical /RAS has fallen. IC20’s selectable inverter chain and IC17 then lower ROW SEL after a delay. IC19 switches from row to column data, preserving row-address hold time first.
4. Column strobe. Delay-line tap Δ1 clocks the other half of IC3. Internal CAS rises; IC10 drives the common /CAS0–3 low. The active bank now has a complete cell address.
5. Data. A read produces one bit per chip on MDI0–7. A write uses buffered MDO0–7 with /WE low; data must satisfy the installed DRAM’s setup and hold requirements around the write-latching edge.
6. Capture and finish. Δ3, its delayed versions, IC4 and the timing straps terminate RAS/CAS. IC12 preserves the read byte after the DRAM outputs release. CYC END also gives the refresh controller a scheduling point. Precharge is required before another RAS pulse.

With a 74LS373 at IC12, its latch-enable is effectively NOT REF CYC AND selected AND RAS: it follows valid DRAM data while enabled and holds it when the window closes. A 74LS374 instead samples on a positive edge derived from Δ3 DELAYED. Straps 12/13 must match the installed part. TI 373/374 datasheet.

The latch’s capture control is separate from its bus output enable. Refresh inhibits capture but is not an input to /OE. During a long selected CPU read, IC12 can keep driving the previously captured byte while the DRAM array is refreshed. Refresh need not force the S-100 data bus to high impedance.

The manual specifies board access times of 450 ns maximum for the 2 MHz board and 250 ns maximum for the 4 MHz board, a listed cycle time of 480 ns maximum, no generated wait states, and DMA at 1 MHz maximum. Those are board specifications, not measured timings here. The text calls for 4116-25 and 4116-20 respectively; the older array drawing says 2117-4 or equivalent. Starred logic positions require 74S parts for the 4 MHz version. Changing only the RAM speed grade does not establish 4 MHz operation.

The STTLDM-401 is drawn with delay taps Δ1, Δ3 and Δ4. No tap delays or tolerance table is included. Straps 5–8 choose end/capture timing; straps 9–11 choose the address-switch delay. The simulator therefore shows phases rather than fabricating exact strobe widths.

Refresh is a second user of the same array

A DRAM read senses and restores an entire internal row even though only one column is presented as data. The 2117 family requires all 128 row addresses to be refreshed within 2 ms. The manual’s 15 µs maximum “refresh period” must be read as a row-service interval: 128 × 15 µs = 1.920 ms, leaving 80 µs against that full-array retention requirement. It is not a claim that an entire array sweep takes 15 µs. Intel 2117 datasheet.

Three Schmitt inverters in IC11, an 82 Ω resistor and a 0.1 µF capacitor form a free-running oscillator. Its edge sets the pending-refresh latch in IC6, producing ALLOW REF. The RC product is 8.2 µs, but that alone is not the oscillator period; thresholds and propagation matter.

At CYC END, the other IC6 flip-flop samples NOT(M1 CYC AND ALLOW REF). A pending request at an instruction-fetch opportunity makes REF CYC high. It clears the request latch, selects IC19’s internal refresh address, and starts a timed refresh operation through IC9/IC10. At completion, REF CYC drops and the 3242 count input advances the row counter. This is a board-local address counter, not the Z80’s refresh-address register.

IC1, a 74LS161, is a watchdog for prolonged waits or reset. Both count enables receive ALLOW REF; its active-low load is NOT(RDY AND /RST), with parallel inputs tied to zero. During normal ready operation it repeatedly loads zero. When RDY or /RST is low, it can count pending-request PCLK edges. Terminal count 15 asserts FORCE REF through IC7, independently forcing the refresh flip-flop into its refresh state. REF CYC then clears the counter. It is not simply a free-running divide-by-16 refresh generator. TI 74LS161 datasheet.

This explains reset straps 14/15: pin 75 or pin 99 must supply the reset signal appropriate to the host. The manual specifically connects a wrong choice with failure to retain data through reset. Power and the required PCLK activity must remain available; this is not battery-backed memory.

/REF RAS = NOT (REF CYC AND internal RAS)
/RAS(bank) = IC22 bank output AND /REF RAS

During refresh, /REF RAS goes low and all four /RAS outputs are forced low through IC23, overriding normal memory selection. Even holes and PHANTOM-disabled areas are restored. Normal reads and writes also refresh their addressed row, but a CPU loop touching a small area does not replace systematic refresh.

Component index

DRAM supplies on A1068 are +5 V on pin 9, +12 V on pin 8, −5 V on pin 1, and ground on pin 16. The placement sheet shows 7805 and 7812 regulators, a 1N4733 zener, a 680 Ω resistor, bulk capacitors and local bypass capacitors. The zener/resistor are consistent with producing the negative bias supply, but these five sheets do not contain a complete power-supply wiring schematic. Verify the actual negative-rail circuit rather than inferring every connection from placement.

Decoupling matters because many DRAM sense amplifiers switch together, especially when all banks refresh. Power faults can look like data or timing faults. Board insertion/removal and component changes must be done with power removed and supplies discharged, as the manual specifies.

A practical sequence of tests

First record the fitted DRAM type, IC12 type, speed version, IC15/16 header wiring, straps 1–15 and all address/hole jumpers. The schematic depicts alternatives, not one universally correct strap configuration.

1. Verify supplies at the DRAM pins. Confirm +5, +12 and −5 V relative to pin 16, then check ripple during accesses and refresh. Check the installed part’s voltage tolerances.
2. Check decode at boundaries. Probe MEM SEL’D at 3FFF/4000, 7FFF/8000 and BFFF/C000. For a SOL-20 hole, also check C7FF/C800 and CFFF/D000. PHANTOM low should disable external access without stopping refresh.
3. Single write/read. Write A5 to 5A3C, read back A5; then try 5A. Under the standard 64 KB map, only /RAS3 should assert on ordinary accesses. MA should change from 43 to 17. /WE goes low on the write; IC12 /OE is low only during the qualified read.
4. Test data bits. Write 01,02,04,08,10,20,40,80 and complements at safe locations in every bank. A repeatable bit failure in one bank implicates that bank’s corresponding DRAM/socket; the same bit across all banks points toward shared MDO, MDI, buffers or IC12.
5. Test address independence. Use address-dependent patterns and walking address bits. Compare 5000/5040 for A6 and 5000/7000 for A13. Compare 1234,5234,9234,D234 with values 11,22,33,44 to expose bank aliasing.
6. Test retention without refreshing the target by reading it. Fill the target, execute elsewhere for several milliseconds, and only then verify. Repeat with reset and a supported wait condition. A tight read loop at the tested addresses can mask a broken refresh system.
7. Probe the refresh chain. Check oscillator edges, ALLOW REF, M1 CYC, CYC END, REF CYC, IC1 carry, and IC19 RF/count. During REF CYC inspect all four /RAS lines and the common /CAS line together. Confirm that 128 distinct row addresses are serviced within the installed DRAM’s refresh requirement.
8. Measure margins. Verify row/column setup and hold, RAS/CAS pulse widths, precharge and IC12 capture relative to data validity using the fitted parts’ datasheets. “No wait states” assumes a compatible CPU bus waveform; it is not permission for arbitrary DMA timing.

The manual’s 8080 test lives in known-good RAM at 0000 and normally tests 4000–7FFF. It writes and verifies a changing byte pattern, offsets it and repeats. On failure it stores the read byte at 0000, expected byte at 0001, low failing-address byte at 0002 and high byte at 0003, then halts. For 32 KB, the manual changes the end comparison bytes at 0016 and 002C to C0. Avoid testing over the running program, stack or active ROM mappings. The printed 2650 test has separate STARTT/ENDT limits and runs from display memory.